Tag: Wind River

5 minute interrupt controller bug chase and fix with Simics

The problem I was writing and testing the interrupt processing code for a real-time hypervisor on the MPC8641 Multi-core PowerPC SoC. During testing, I hit a bug: the system would not take any more interrupts after the highest priority interrupt got serviced. Since I was debugging on the Wind River Simics virtual platform, debugging the […]

Easy multi-core PowerPC timebase synchronization with Simics

The problem When writing low-level multi-core OS code, it is important that all cores have at least some form of time synchronization so that scheduling can be done using local timers. On 32-bit PowerPCs, this is usually accomplished by making sure the 64-bit Time Base register (made up of TBL and TBU, the lower and […]